1. Field of the Invention
The present invention relates in general to integrated circuit (IC) testers and in particular a parallel processing pattern generation system for an IC tester.
2. Description of Related Art
A typical per-pin integrated circuit tester includes a set of tester channels, one for each pin of an integrated circuit device under test (DUT). The tester organizes a test into a set of successive test cycles, and during each test cycle each channel carries out a test activity at a corresponding DUT pin. For example a tester channel may supply a test signal input to the DUT terminal or may monitor a DUT output signal at the terminal and produce an indicating "FAIL" signal when the DUT output signal does not behave as expected. The tester includes a pattern generator for supplying input data to each tester channel telling the tester channel what to do during each test cycle. The input data may also indicate expected states of DUT output signals during a test cycle.
Early pattern generators consisted primarily of a large addressable memory addressed by a counter. Each storage location of the memory contained all of the data needed for one cycle of the test and data for successive test cycles was stored at successive memory addresses. The counter incremented its output count for each successive test cycle so that the memory read out the appropriate pattern data for that cycle. As the size and complexity of integrated circuits increased, the required width and depth of the pattern memory became excessively large.
To reduce the amount of memory needed to store data defining a test, some integrated circuit testers were designed to store sequences of "vectors" referencing channel data patterns instead of channel data patterns themselves. As each vector is read out of memory it was decoded to produce the appropriate channel data pattern. This reduced the width, though not the depth, of the required pattern memory.
Some integrated circuit testers store algorithmic instructions for generating a vector sequence instead of the vector sequence itself. These testers include processors capable of executing those instructions to produce vector sequences during the test. In tests in which portions of a sequence of vectors are repetitive, an algorithm for generating such a vector sequence requires fewer memory storage locations than the vector sequence itself. However algorithmic vector sequence generation typically does not save much memory when the vector sequence to be generated is complex and non-repetitive. Also, the nature of the algorithm, and the nature of the processor needed to execute it, depend on the nature of the device being tested and on the nature of the test being performed. Thus, algorithmic pattern generators are typically designed with specific tests in mind and are not used in general purpose testers.
Thus the efficiency and ease with which an integrated circuit tester can be programmed to carry out a test depends largely on matching the type of pattern generator it employs to the nature of test it is being performed. A general purpose tester capable of efficiently carrying out a wide variety of integrated circuit tests has been elusive.